The present invention is related to logic devices, and more particularly to differential logic devices.
Differential Emitter coupled logic has been used to create multiple input stacked gates. As an example, FIG. 1 shows a two input differential AND gate 100 implemented in emitter coupled logic. As shown, AND gate 100 includes two differential input pairs 107, 111, with one stacked upon the other. One pair of differential inputs 132, 134 are applied to the respective bases of a transistor 106 and a transistor 108 of differential pair 107. Another pair of differential inputs 136, 138 are applied to the respective bases of a transistor 110 and a transistor 112 of differential pair 111. Both differential pair 107 and differential pair 111 are biased by the same current source generated by applying a bias voltage 140 to a transistor 116 that is electrically coupled to ground (VSS 142) via a resistor 114. The collector of transistor 106 is electrically coupled to VDD 130 via a resistor 102, and to the base of an emitter follower transistor 128. The collector of transistor 108 is electrically coupled to VDD 130 via a resistor 104, and to the base of an emitter follower transistor 126. The collector of transistor 112 is also electrically coupled to the base of emitter follower transistor 126. The collector of transistor 110 is electrically coupled to the emitters of transistor 106 and transistor 108. Resistor 102 and resistor 104 are the same value. Emitter follower transistor 126 is biased by a transistor 120 and a resistor 118, and emitter follower transistor 128 is biased by a transistor 124 and a resistor 122. Two sets of differential outputs are provided from AND gate 100: an upper biased pair including Y 184 and YZ 182; and a lower biased pair including YEFZ 186 and YEF 188. As the input bias required into each stage may be slightly different, the two pairs of differential outputs are necessary depending upon the next stage to be driven. This is one of the significant disadvantages of differential emitter coupled logic.
In operation, when both input 132 is asserted high relative to input 134, and input 136 is asserted high relative to input 138, output Y 184 is asserted high with respect to output YZ 182 and output YEF 188 is asserted high with respect to output YEFZ 186. In this case, transistor 106 and transistor 110 are turned on, and the tail current sourced by transistor 114 traverses resistor 102, transistor 106 and transistor 110. No current traverses resistor 104 as transistor 108 and transistor 112 are turned off. Thus, the voltage level at the base of emitter follower transistor 128 (Vb is VDD−Itail*R102) is lower than that at the base of emitter follower transistor 126 (Vb is near VDD 130). Thus, YEF 188 is greater than YEFZ 186 indicating a logic ‘1’ value. In contrast, where either or both of input 132 or input 136 are asserted low relative to input 134 or input 138, respectively, the tail current sourced by transistor 114 traverses resistor 104, and no current traverses resistor 102. Thus, the voltage level at the base of emitter follower transistor 126 (Vb is VDD−Itail*R104) is lower than that at the base of emitter follower transistor 128 (V is near VDD 130).
One problem with the design of AND gate 100 is that considerable head room is needed between VDD 130 and VSS 142 as there are voltage drops through three transistors and through two resistors. This headroom limitation becomes more acute as additional inputs are added to a particular gate. For example, a three input AND gate includes an additional stacked differential input. In such a case, there are voltage drops through four transistors and through two resistors. Thus, such an approach to logic gates is severely limited in the number of inputs that may be handled in the same logic gate. Further, such an approach to logic gates requires the use of higher voltage power supplies, which can be a disadvantage in many design situations.
As another example of the same emitter coupled logic architecture, FIG. 2 shows a three input differential OR gate 200. As shown, OR gate 200 includes three differential input pairs 207, 211, 215 each stacked one upon the other. One pair of differential inputs 232, 234 is applied to the respective bases of a transistor 206 and a transistor 208 of differential pair 207. Another pair of differential inputs 236, 238 is applied to the respective bases of a transistor 210 and a transistor 212 of differential pair 211. Yet another pair of differential inputs 240, 242 is applied to the respective bases of a transistor 214 and a transistor 216 of differential pair 215. Each of differential pair 207 differential pair, 211 and differential pair 215 are biased by the same current source generated by applying a bias voltage 244 to a transistor 218 that is electrically coupled to ground (VSS 246) via a resistor 220. The collector of transistor 206 is electrically coupled to VDD 230 via a resistor 202, and to the base of an emitter follower transistor 231. The collector of transistor 208 is electrically coupled to VDD 230 via a resistor 204, and to the base of an emitter follower transistor 229. The collectors of transistor 212 and of transistor 216 are also electrically coupled to the base of emitter follower transistor 229. The collector of transistor 210 is electrically coupled to the emitters of transistor 206 and transistor 208. The collector of transistor 214 is electrically coupled to the emitters of transistor 210 and transistor 212. Resistor 202 and resistor 204 are the same value. Emitter follower transistor 229 is biased by a transistor 224 and a resistor 222, and emitter follower transistor 231 is biased by a transistor 228 and a resistor 226. Two sets of differential outputs are provided from OR gate 200: an upper biased pair including Y 282 and YZ 284; and a lower biased pair including YEFZ 288 and YEF 286. Again, the need for two sets of differential outputs is a disadvantage of the existing emitter coupled logic architecture. The three pairs of input differential pairs 207, 211, 215 likewise require input signals that are offset at three differential common mode levels.
In operation, when all of input 232, input 236 and input 240 are asserted high with respect to inputs 234, 238, 242, respectively; the tail current tail current sourced by transistor 218 traverses resistor 202, and no current traverses resistor 204. In this condition, the voltage level at the base of emitter follower transistor 231 (V is VDD−Ytail*R202) is lower than that at the base of emitter follower transistor 229 (V is near VDD 230). Thus, YEFZ 288 is greater than YEF 286. In contrast, where any of input 232, input 236 and/or input 240 is/are asserted low with respect to inputs 234, 238, 242, respectively; the tail current sourced by transistor 218 traverses resistor 204, and no current traverses resistor 202. Thus, the voltage level at the base of emitter follower transistor 229 (V is VDD−Ytail*R104) is lower than that at the base of emitter follower transistor 231 (V is near VDD 130).
Three input OR gate 200 has the same problem as the previously discussed two input AND gate in that considerable head room is needed between VDD 230 and VSS 246 as there are voltage drops through four transistors and through two resistors. This headroom limitation becomes more acute as additional inputs are added to a particular gate. For example, a four input OR gate includes an additional stacked differential input. In such a case, there are voltage drops through five transistors and through two resistors. Thus, such an approach to logic gates is severely limited in the number of inputs that may be handled in the same logic gate. Further, such an approach to logic gates requires the use of higher voltage power supplies, which can be a disadvantage in many design situations.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced logic architectures.